NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 102

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
3.8.7
Table 3-32. When Will a Intel 5000P Chipset PCI Express Device be Accessible?
102
PCI Express Device Configuration Registers
This section describes the registers associated with the PCI Express Interface.
The PCI Express register structure is exposed to the operating system and requires a
separate device per port. Ports 2-7 will be assigned devices 2 through 7 while Port 0 is
the ESI interconnect to the Intel 631xESB/632xESB I/O Controller Hub. The PCI
Express ports determine at reset the maximum width of the devices to which they are
connected through link training. All ports will be made visible to OS even if
unconnected. If Ports are combined to form larger widths (for example, x8 or x16 from
a x4 link), then the unused ports will Master Abort (reads return all ones, writes
dropped) any accesses to it. Note that configuration accesses to the unconnected port
will still be allowed to permit device remapping, hot-plug and so forth.
(Sheet 1 of 2)
Device:
Function:
Offset:
Version:
30:24
22:20
19:16
Express
15:8
7:0
Bit
31
23
Port
PCI
7
6
5
4
if (XTPR0)
{RW}
else {RV}
endif
Attr
RW
RW
RW
RW
RV
RV
Device
16
0
BCh, B8h, B4h, B0h, ACh, A8h, A4h, A0h, 9Ch, 98h, 94h, 90h, 8Ch, 88h, 84h, 80h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
7
6
5
4
Default
possible
combination
possible
combination
00h
0h
0h
0h
0h
0
0
x8
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
CLUSTER: Global Cluster Mode (XTPR[0] only)
Used in interrupt redirection for lowest priority delivery. Updated by every
xTPR_Update transaction on either bus (Aa[3]).
0: flat
Note: Cluster Mode not Supported
Reserved.
TPREN: TPR Enable
This bit reflects the value of Ab[31]#. When Ab[31]# is asserted, the value
of this bit will be 0.
Reserved.
PRIORITY: Task Priority
The processor with the lowest enabled value will be assigned the
redirectable interrupt. This field is updated with Ab[27:24] of the
xTPR_Update transaction.
PHYSID: Physical APIC ID
The physical ID of the APIC agent associated with the XTPR entry. This field
is updated with Aa[19:12] of the xTPR_Update transaction.
LOGID: Logical APIC ID
The logical ID of the APIC agent associated with the XTPR entry. This field
is updated with Aa[11:4] of the xTPR_Update transaction.
Port 7 is connected to a x4 device
Port6 is connected to a x4 or x8 device
Port5 is connected to a 4x device
Port 4 is connected to connected to a x4 or x8 device
Registers may be accessed if:
Description
Register Description

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