NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 109

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.8.5
3.8.8.6
3.8.8.7
3.8.8.8
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
BIST[7:2,0] - Built-In Self Test
This register is used for reporting control and status information of BIST checks within
a PCI Express port. It is not supported in the Intel 5000P Chipset MCH.
BAR0[7:2,0] - Base Address Register 0
Base address registers are used for mapping internal registers to an MMIO or I/O
space. It does not affect the MCH. The base address register 0 is not supported/defined
in the PCI Express port of the MCH.
BAR1[7:2,0] - Base Address Register 1
The base address register 1 is not supported/defined in the MCH.
EXP_ROM[0]: Expansion ROM Registers
The ESI port (device 0, function 0) does not implement any Base address registers in
the Intel 5000P Chipset MCH from offset 10h to 24h. Similarly no Expansion ROM base
address register is defined in offset 30h. Also no Cardbus CIS pointer is defined in
offset 28h. The MIN_GNT (offset 3Eh) and MAX_LAT (3Fh) registers are also not
implemented as they are not applicable to the ESI interface.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:0
7:0
Bit
Bit
Attr
Attr
RO
RO
0, 2-3
0
0Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
0Dh
Intel 5000Z Chipset
4-7
0
0Dh
Intel 5000P Chipset
0, 3-2
0
0Fh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
0Fh
Intel 5000Z Chipset
7-4
0
0Fh
Intel 5000P Chipset
Default
Default
00h
00h
Prim_Lat_timer: Primary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.
BIST_TST: BIST Tests
Not supported. Hardwired to 00h
Description
Description
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