NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 11

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
3-36 Negotiated Link Width For Different PCI Express Ports After Training ...................... 150
3-37 Global Activation Throttling as a Function of Global Activation
3-38 FB-DIMM to Host Gear Ratio Mux....................................................................... 199
3-39 FB-DIMM to Host Gear Ratio Mux....................................................................... 199
3-40 Host to FB-DIMM Gear Ratio Mux Select ............................................................. 200
3-41 FB-DIMM Host Data Cycle Valid Mux Select ......................................................... 201
3-42 FB-DIMM to Host Flow Control Mux Select........................................................... 202
3-43 FB-DIMM Bubble Mux Select ............................................................................. 202
3-44 FB-DIMM to Host Double Config Mux Select ........................................................ 203
3-45 Optimum TREF values as a function of core: FBD gear ratios
3-46 Timing Characteristics of ERRPER ...................................................................... 206
3-47 Interleaving of an address is governed by MIR[i] ................................................. 207
3-48 NRECFBD Mapping Information ......................................................................... 218
3-49 ECC Locator Mapping Information ...................................................................... 220
3-50 IV Vector Table for DMA Errors and Interrupts..................................................... 262
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10 Address Disposition for Inbound Transactions...................................................... 292
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10 Global Activation Throttling BW allocation as a function of GBLACTLM for a
5-11 Electrical Throttle Window as a Function of DIMM Technology ................................ 326
5-12 XAPIC Data Encoding ....................................................................................... 328
5-13 Intel 5000P Chipset XAPIC Interrupt Message Routing and Delivery ....................... 329
5-14 Chipset Generated Interrupts............................................................................ 337
5-1
5-15 Options and Limitations.................................................................................... 347
5-16 PCI Express Credit Mapping for Inbound Transactions .......................................... 352
5-17 PCI Express Credit Mapping for Outbound Transactions ........................................ 353
5-18 MCH Reset Classes .......................................................................................... 356
5-19 Reset Sequences and Durations ........................................................................ 359
5-20 SMBus Transaction Field Summary .................................................................... 361
5-21 SMBus Address for Product Name Platform ......................................................... 367
Throttling Limit (GBLACTM) and Global Throttling Window Mode
(GTW_MODE) Register Fields ............................................................................ 194
(in FBD Super frames) ..................................................................................... 205
Memory Segments and Their Attributes .............................................................. 278
PAM Settings .................................................................................................. 280
Low Memory Mapped I/O1 ................................................................................ 283
I/O APIC Address Mapping................................................................................ 285
Intel 5000P Chipset MCH Memory Mapping Registers ........................................... 287
Address Disposition for Processor ...................................................................... 288
Enabled SMM Ranges ....................................................................................... 290
SMM Memory Region Access Control from Processor............................................. 290
Decoding Processor Requests to SMM and VGA Spaces ......................................... 291
DBI[3:0]# / Data Bit Correspondence ................................................................ 298
Minimum System Memory Configurations & Upgrade Increments ........................... 299
Maximum 16 DIMM System Memory Configurations ............................................. 300
Maximum 16 DIMM System Memory Configurations ............................................. 300
Memory Poisoning Table................................................................................... 307
x8 Double Device Detection Characteristics......................................................... 309
SPD Addressing............................................................................................... 310
AMB Thermal Status Bit Definitions .................................................................... 316
FB_DIMM Bandwidth as a Function of Closed Loop Thermal Throttling .................... 322
16384**1344 window with MC.GTW_Mode=0 (normal) ........................................ 325
PCI Express Link Width Strapping Options for Port CPCI
Configuration in MCH ....................................................................................... 347
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