NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 115

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.8.16
3.8.8.17
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
MBASE[7:2] - Memory Base
The Memory Base and Memory Limit registers define a memory mapped I/O non-
prefetchable address range (32-bit addresses) and the MCH directs accesses in this
range to the PCI Express port based on the following formula:
The upper 12 bits of both the Memory Base and Memory Limit registers are read/write
and corresponds to the upper 12 address bits, AD[31:20], of 32-bit addresses. For the
purpose of address decoding, the bridge assumes that the lower 20 address bits,
AD[19:0], of the memory base address are zero. Similarly, the bridge assumes that the
lower 20 address bits, AD[19:0], of the memory limit address (not implemented in the
Memory Limit register) are FFFFFh. Thus, the bottom of the defined memory address
range will be aligned to a 1 MB boundary and the top of the defined memory address
range will be one less than a 1 MB boundary. Refer to
Section 4.4.3
address mapping.
MLIM[7:2]: Memory Limit
This register controls the processor to PCI Express non-prefetchable memory access
routing based on the following formula as described above:
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh.
Memory range covered by MBASE and MLIM registers, are used to map non-
prefetchable PCI Express address ranges (typically where control/status memory-
mapped I/O data structures reside) and PMBASE and PMLIM are used to map
prefetchable address ranges. This segregation allows application of USWC space
attribute to be performed in a true plug-and-play manner to the prefetchable address
range for improved PCI Express memory access performance.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:4
3:0
Bit
MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT
Attr
RW
RO
2-3
0
20h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
20h
Intel 5000Z Chipset
4-7
0
20h
Intel 5000P Chipset
in the Intel 5000P Chipset programmer’s guide for further details on
Default
0h
0h
MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT
MBASE: Memory Base Address
Corresponds to A[31:20] of the memory address on the PCI Express port.
Reserved. (by PCI SIG)
Description
Section
4.3.9,
Section 4.4.2
and
115