NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 118

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.8.20
118
PMBU[7:2] - Prefetchable Memory Base (Upper 32 bits)
The Prefetchable Base Upper 32 bits and Prefetchable Limit Upper 32 bits registers are
extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
If the Prefetchable Memory Base and Prefetchable Memory Limit registers indicate
support for 32-bit addressing, then the Prefetchable Base Upper 32 bits and
Prefetchable Limit Upper 32 bits registers should return zero when read. If the
Prefetchable Memory Base and Prefetchable Memory Limit registers indicate support for
64-bit addressing, then the Prefetchable Base Upper 32 bits and Prefetchable Limit
Upper 32 bits registers are implemented as read/write registers.
If a 64-bit prefetchable memory address range is supported, the Prefetchable Base
Upper 32 bits and Prefetchable Limit Upper 32 bits registers specify the upper 32 bits,
corresponding to A[63:32], of the 64-bit base and limit addresses which specify the
prefetchable memory address range.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:0
3:0
Bit
Bit
Attr
Attr
RW
RO
2-3
0
26h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-7
0
26h
Intel 5000P Chipset
2-3
0
28h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
28h
Intel 5000Z Chipset
4-7
0
28h
Intel 5000P Chipset
Default
Default
1h
0h
PMLIMIT_CAP: Prefetchable Memory Limit Address Capability
0h – 32 bit Prefetchable Memory addressing
1h – 64 bit Prefetchable Memory addressing,
others - Reserved.
PUMBASE: Prefetchable Upper 32-bit Memory Base Address
Corresponds to A[63:32] of the memory address that maps to the upper base
of the prefetchable range of memory accesses that will be passed by the PCI
Express bridge. OS should program these bits based on the available physical
limits of the system.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description