NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 119

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.8.21
3.8.8.22
3.8.8.23
3.8.8.24
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PMLU[7:2] - Prefetchable Memory Limit (Upper 32 bits)
IOB[7:2] - I/O Base Register (Upper 16 bits)
Not used since MCH does not support upper 16-bit I/O addressing.
IOL[7:2] - I/O Limit Register (Upper 16 bits)
Not used since MCH does not support upper 16-bit I/O addressing.
CAPPTR[7:2, 0]- Capability Pointer
The CAPPTR is used to point to a linked list of additional capabilities implemented by
this device.
It provides the offset to the first set of capabilities registers located in the PCI
compatible space from 40h. Currently the first structure is located 50h to provide room
for other registers.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:0
7:0
Bit
Bit
Attr
Attr
RW
RO
2-3
0
2Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
2Ch
Intel 5000Z Chipset
4-7
0
2Ch
Intel 5000P Chipset
0, 2-3
0
34h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
34h
Intel 5000Z Chipset
4-7
0
34h
Intel 5000P Chipset
Default
Default
50h
0h
PUMLIM: Prefetchable Upper 32-bit Memory Limit Address
Corresponds to A[63:32] of the memory address that maps to the upper limit of
the prefetchable range of memory accesses that will be passed by the PCI
Express bridge. OS should program these bits based on the available physical
limits of the system.
CAPPTR: Capability Pointer
Points to the first capability structure (PM) in PCI 2.3 compatible space at 50h
Description
Description
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