NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 121

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Register Description
3.8.8.28
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
BCTRL[7:2] - Bridge Control Register
This register provides extensions to the PCICMD register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (that is, PCI
Express) as well as some bits that affect the overall behavior of the “virtual”
PCI-PCI bridge embedded within the MCH, for example, VGA compatible address
range mapping.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:12
Bit
11
10
9
8
7
6
Attr
RW
RO
RO
RO
RO
RO
RV
2-3
0
3Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Eh
Intel 5000Z Chipset
4-7
0
3Eh
Intel 5000P Chipset
Default
0h
0
0
0
0
0
0
Reserved. (by PCI SIG)
DTSS: Discard Timer SERR Status
Not applicable to PCI Express. This bit is hardwired to 0.
DTS: Discard Timer Status
Not applicable to PCI Express. This bit is hardwired to 0.
SDT: Secondary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
PDT: Primary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
FB2BEN: Fast Back-to-Back Enable
Not applicable to PCI Express. This bit is hardwired to 0.
SBUSRESET: Secondary Bus Reset
1:
Express
This sends the LTSSM into the Hot-Reset state, which necessarily implies a
reset to the downstream device and all subordinate devices.
The mechanism to reset the downstream device is utilizing the TS1/TS2 “link
reset” bit (bit number 0 of symbol 5). It is recommended for software/BIOS
that the SBUSRESET field be held asserted for a minimum of 2 ms to ensure
that the Link enters the Hot-Reset state from L0 or L1/L2.
Software can also poll the PEXLNKSTS.LNKTRG bit for a deasserted condition
to determine if the hot-reset state has been entered at which point it can clear
the SBUSRESET field to train the link.
When this SBUSRESET bit is cleared after the MCH enters the “hot-reset”
state, the Intel 5000P Chipset MCH will initiate operations to move to “detect”
state and then train the link (polling, configuration, L0 (link-up)) after sending
at least 2 TS1 and receiving 1 TS1 with the HotReset bit set in the training
control field of TS1 and waiting for 2ms in the Hot-reset state. The 2ms stay in
the Hot-reset state is enforced by the chipset LTSSM for the PCI Express
hierarchy to reset.
If the SBUSRESET is held asserted even after the 2ms time-out has expired,
the Intel 5000P Chipset MCH will continue to maintain the hot-reset state.
Hence it is necessary for software to clear this register appropriately to bring
the link back in training.
Note also that a secondary bus reset will not in general reset the primary side
configuration registers of the targeted
allow software to specify special training configuration, such as entry into
loopback mode.
0: No reset happens on the PCI Express port.
Setting this bit causes a hot reset on the link for the corresponding
port and the
PCI Express
Description
hierarchy domain subordinate to the port.
PCI Express
port. This is necessary to
PCI
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