NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 126

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.8.30
126
PEXCTRL[7,2:0]: PCI EXPRESS Control Register
Device:
Function: 0
Offset:
31:26
25:24
Bit
23
22
7-2,0
48h
Attr
RW
RW
RW
RW
Default
0h
00
0
0
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Reserved
COALESCE_MODE: Used to increase the amount of combining for
completions.
00: No restriction on coalescing_hint. The IOU will try to maximize
completion combining. Since Intel 5000P Chipset MCH issues requests
in order, it does not make sense to restrict the coalesce hint because
there are few resources available at the time of fetch. By the time the hint
is used, resources could be freed up and reused for the following
requests.
Note: This mode of “00” is the preferred setting for Intel 5000P
Chipset MCH if COALESCE_EN=1 for software/BIOS
01: #CPL_ENTRIES_FREE will restrict coalesce_hint
10: if set then #PF_PEND will restrict coalesce hint
11: Minimum of coalesce_hint obtained from settings “01” and “10”
TIMEOUT_ENABLE_CFG: Timeout enable for configuration
transactions
1: Config transactions can time out.
0: Config transactions cannot time out.
Suggested value: 0
Note:
Note:
Note:
TIMEOUT_ENABLE: Timeout enable for non-configuration
transactions
1: Non config transactions can time out.
0: Non config transactions cannot time out.
Suggested value: 1
Note:
Note:
In general, configuration timeouts on the PCI-Express port
should not be enabled. This is necessary to permit slow devices
nested deep in the PCI hierarchy that may take longer to
complete requests than the maximum timeout specified in the
Intel 5000P. Software/BIOS should set this field based on the
context and usage/platform configuration. For e.g. compliance
testing with a known broken card should have this field set.
For the configuration timeout to take effect, (due to Intel 5000P
RTL implementation) the PEXCTRL.TIMEOUT_ENABLE (bit 22)
has to be set.
Due to recently discovered RTL bug in B3 and later stepping, the
IOU will log a completion error (IO6) for any outstanding
configuration transaction that crosses the counter limit even if
this register field is cleared or bit 22 of this register is cleared
(Example, either timeout is disabled. However, it does not affect
the functionality and the config transaction will be outstanding
indefinitely until the completion is returned except for the
unnecessary error log. Software should be aware of this
limitation when the field is cleared.)
When both TIMEOUT_ENABLE_CFG and TIMEOUT_ENABLE fields
are set to 0, the Intel 5000P will assume an infinite completion
time for the respective transactions. Hence the system is
dependent on the end device returning the completion response
at some point in time, else it will result in a hang.
Due to recently discovered RTL bug in B3 and later stepping, the
IOU will log a completion error (IO6) for any outstanding
configuration transaction that crosses the counter limit even if
this register field is cleared or bit 22 of this register is cleared
(Example, either timeout is disabled. However, it does not affect
the functionality and the config transaction will be outstanding
indefinitely until the completion is returned except for the
unnecessary error log. Software should be aware of this
limitation when the field is cleared.)
Description
Register Description