NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 127

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Device:
Function: 0
Offset:
20:13
Bit
21
12
11
10
9
8
7
7-2,0
48h
Attr
RW
RW
RW
RW
RW
RW
RV
RV
Default
0h
0
0
0
0
0
0
1
MALTLP_EN:
1: Check for certain malformed TLP types.
0: Do not check for certain malformed TLP types.
Suggested value: 1
When this bit is set, it enables the following conditions to mark a packet
as malformed:
Reserved
Max_rdcmp_lmt_EN: Maximum Read completion combining limit
Enable
1: Up to 256 B return and COALESCE_EN = 1.
0: Up to 128 B return if COALESCE_EN = 1
Note: It is strongly recommended that this field should not be set to 1
(256 B completion combining) due an MCH B2 silicon issue, especially
when MPS is configured to 256 B.
COALESCE_FORCE: Force coalescing of accesses.
When 1, forces Intel 5000P Chipset MCH to wait for all coalescable data
before sending the transaction as opposed to forwarding as much as
possible.
0: Normal operation
1: wait to coalesce data
Note: It is strongly recommended that COALESCE_FORCE should not be
set to ‘1’ due to an MCH B2 silicon erratum.
COALESCE_EN: Read completion coalescing enable
When 1, enables read return of >64 B.
1: Returns of >64 B enabled. (See Max_rdcmp_lmt_EN above).
0: Returns are 64 B or less.
NOTE: For optimal read completion combining, this field should be set to
‘1’ along with Max_rdcmp_lmt_EN as ‘0’ for 128B completion
combining.
PMEGPEEN: PME GPE Enable
1: Enables “assert_pmegpe” (deassert_pmegpe) messages to be sent
over the DMI from the root complex for PM interrupts.
0: Disables “assert_pmegpe” (deassert_pmegpe) messages for PM
events to the root complex.
This has an overriding effect to generate ACPI PM interrupts over
traditional interrupts (MSI/intx).
HPGPEEN: Hotplug GPE Enable
1: Enables “assert_hpgpe” (deassert_hpgpe) messages to be sent from
the root complex for Hot-plug events.
0: Disables “assert_hpgpe” (deassert_hpgpe) messages for Hot-plug
events from the root complex.
This has an overriding effect to generate ACPI HP events over traditional
interrupts.
Reserved
• 4DW header MEM_RD or MEM_WR and the address is less than 32
• Byte enable check for mem/io/cfg requests. Length > 1 DW and
• IO{rd,wr}/cfg{rd,wr}{0,1} and (traffic class != 0 or attributes != 0
• A configuration retry completion response (CRS) received for a non-
bits (address[39:32] = 0)
(first dword byte enables = 0 or last dword byte enables = 0) Length
= 1 DW and last dword byte enables != 0
or length != 1)
cfg outbound request
Description
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