NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 128

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

128
This 32-bit register implements chipset specific operations for general control/
accessibility such as device hiding, selective configuration cycles and interrupt signaling
Device:
Function: 0
Offset:
6:3
Bit
2
1
0
2) {RWO}
if (port 7-
elsif (port
0) {RV}
7-2,0
48h
endif
Attr
RW
RW
RW
Default
0000
1
0
0
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
VPP: Virtual Pin Port
[6:4] = SMBus Address, [3] =IO Port
defines the 8-bit IO port that is used for routing power, attention,
Hotplug, presence, MRL and other events defined in
DIS_VPP: Disable VPP
The Intel 5000P Chipset MCH will use this bit to decide whether the VPP
is valid or not for the given PCI Express port as set by configuration
software. For example, to distinguish HP events for a legacy card or PCI
Express port module, this bit can be used.
1: VPP is disabled for this PCI Express port.
0: VPP is enabled for this PCI Express port.
Default value is to disable vpp for the PCI Express port
DIS_APIC_EOI; Disable APIC EOI
The
interrupts (EOI) need to be sent to an APIC controller/bridge (for
example, Intel 6700PXH 64 bit PCI Hub) through this PCI Express
device.
1: no EOIs are sent (disabled).
0: EOIs are dispatched to the APIC Controller.
Note:
DEVHIDE: Device_hide
The device hide bit is used to enable the Intel 5000P Chipset
the PCI Express device from the Operating system and is applicable only
to ports 7-2. Typically, an external I/O processor acts as its proxy by
configuring it and claiming resources on behalf of it and then unhides.
The hiding is done by changing the class code (CCR register) for this port
to 0x0600. This will prevent the OS from attempting to probe or modify
anything related to this device.
1: The PCI Express port CCR register has a value of 0600.
0: The PCI Express port CCR register has a value of 0604 (bridge)
The default value is ‘0’ (to make the device a bridge).
The device hide bit does not apply to the DMI interface (port 0) and has
no effect on its operation.
Intel 5000P Chipset
In the case of slave (secondary) ports, the BIOS has to disable
EOI for that port by setting this register field. For example, x8
device connected on port 2-3 should have the
PEXCTRL.DIS_APIC_EOI of the slave port (viz. #3) set to
prevent EOIs from causing deadlocks. This is a micro-
architectural requirement due to the internal handshake
between IOU-CE for EOI slave handling.
MCH will use this bit to decide whether end of
Description
Register Description
Section
MCH to hide
3.8.11.10.