NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 129

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.8.31
3.8.8.32
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PEXCTRL2[7:2,0]: PCI Express Control Register 2
This is an auxiliary control register for PCI Express port specific debug/defeature
operations.
PEXCTRL3[7:2,0] - PCI Express Control Register 3
This is an additional control register for PCI Express port specific debug/defeature
operations for RAS.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:1
7:5
3:0
Bit
Bit
0
4
Attr
RW
RV
RWO
Attr
RV
RV
0, 2-3
0
4Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
4Ch
Intel 5000Z Chipset
4-7
0
4Ch
Intel 5000P Chipset
0, 2-3
0
4Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
4Dh
Intel 5000Z Chipset
4-7
0
4Dh
Intel 5000P Chipset
Default
0
0
Default
0
1
0
Reserved.
NO_COMPLIANCE:
Set by software to enable link operation in the presence of single wire failures
on the link. If clear, then specified link behavior in the presence of a wire failure
will be Polling.Compliance.
Reserved.
PORTENABLE: PCI Express port enable control
1: The PCI Express port can be enabled by software and is available for
use.
0: The PCI Express port is disabled and not available. This setting disables
the underlying port logic and associated PCI Express x4 lanes, completely
removing the port from register configuration space.
Reserved
Description
Description
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