NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 131

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.8.34
3.8.9
3.8.9.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
INTXSWZCTRL[7:2,0]: PCI Express Interrupt Swizzle Control Register
This register provides software the ability to swizzle the legacy interrupts (intx) from
each port and remap them to a different interrupt type (IntA,B,C,D) for the purposes of
interrupt rebalancing to optimize system performance. This swizzling only applies to
inbound intx messages that arrive at the various ports (including ESI). The default
setting is to have one-to-one map of the same interrupt types, that is (INTA => INTA,
and so forth). BIOS can program this register during boot time (before enabling
interrupts) to swizzle the intx types for the various ports within the combinations
described in this register. MCH will use the transformed intx messages from the various
ports and track them using the bit vector as a wired-or logic for sending assert/
deassert intx messages on the ESI. Please refer to the Interrupt Swizzling Solution for
Intel 5000 Chipset Series-based Platforms - Applicaiton Note, document #314337
available on developer.intel.com for more detailed information on this feature.
PCI Express Power Management Capability Structure
The Intel 5000P Chipset MCH PCI Express port provides basic power management
capabilities to handle PM events for compatibility. The PCI Express ports can be placed
in a pseudo D3 hot state but it does have real power savings and works as if it were in
the D0 mode.
PMCAP[7:2,0] - Power Management Capabilities Register
The PM Capabilities Register defines the capability ID, next pointer and other power
management related support. The following PM registers /capabilities are added for
software compliance.
Device:
Function: 0
Offset:
7:2
1:0
Bit
RWO
Attr
7-2,0
4Fh
RO
Default
0h
00
Reserved
INTxSWZ: INTx Swizzle
The encoding below defines the target Intx type to which the incoming Intx
message is mapped to for that port. (4 combinations using the Barber-pole
slide mechanism)
00: INTA=>INTA, INTB=>INTB, INTC=>INTC, INTD=>INTD (default 1:1)
01: INTA=>INTB, INTB=>INTC, INTC=>INTD, INTD=>INTA
10: INTA=>INTC, INTB=>INTD, INTC=>INTA, INTD=>INTB
11: INTA=>INTD, INTB=>INTA, INTC=>INTB, INTD=>INTC
Description
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