NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 135

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Register Description
3.8.10.3
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
MSICTRL[7:2, 0] - Message Control Register
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:8
6:4
3:1
Bit
7
0
Attr
RW
RW
RO
RO
RV
0, 2-3
0
5Ah
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
5Ah
Intel 5000Z Chipset
4-7
0
5Ah
Intel 5000P Chipset
Default
00h
000
001
0
0
Reserved.
AD64CAP: 64-bit Address Capable
This field is hardwired to 0h since the message writes addresses are only 32-
bit addresses (for example, FEEx_xxxxh).
MMEN: Multiple Message Enable
Software writes to this field to indicate the number of allocated messages
which is aligned to a power of two. When MSI is enabled, the software will
allocate at least one message to the device. See below for discussion on how
the interrupts are handled if N is the number of messages by software.
If software writes a value greater than the limit specified by the MMCAP field in
the MMEN field, it is considered as a programming error. The Intel 5000P
Chipset MCH GNB will only use the LSB of the MMEN (as a power of 2) to
decode up to 2 messages.
MMCAP: Multiple Message Capable
Software reads this field to determine the number of requested messages.
which is aligned to a power of two. It is set to 2 messages (encoding of 001).
Th
MSIEN: MSI Enable
The software sets this bit to select legacy interrupts or transmit MSI
messages.
0: Disables MSI from being generated.
1: Enables the Intel 5000P Chipset MCH to use MSI messages to request
context specific service through register bits defined in the
for events such as hot-plug, PM, RAS.
Refer to the Intel 5000P Chipset Programming Guide for details on the legacy,
ACPI and interrupt generation events.
e Intel 5000P Chipset MCH is designe
HP/PM events
RAS Error events
Description
d to handle MSIs for different events
Section 3.8.8.32
135

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