NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 137

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
Table 3-34. IV Handling and Processing by MCH
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
a. The term “xxxxxx” in the Interrupt vector denotes that software/BIOS initializes them
Notes:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
13:11
10:8
7:0
Number of Messages
enabled by Software
and the MCH will not modify any of the “x” bits except the LSB as indicated in the table
as a function of MMEN
Bit
15
14
(MSICTRL.MMEN)
Attr
RW
RW
RW
RW
RW
1
2
0, 2-3
0
60h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
60h
Intel 5000Z Chipset
4-7
0
60h
Intel 5000P Chipset
Default
0h
0h
0h
0h
0h
TM: Trigger Mode
This field Specifies the type of trigger operation
0: Edge
1: level
LVL: Level
If TM is 0h, then this field is a don’t care.
Edge triggered messages are consistently treated as assert messages. For
level triggered interrupts, this bit reflects the state of the interrupt input if TM
is 1h, then
0: Deassert Messages
1: Assert Messages
DM: Delivery Mode
000: Fixed
001: Lowest Priority
010: SMI/HMI
011: Reserved
100: NMI
101: INIT
110: Reserved
111: ExtINT
IV: Interrupt Vector
The interrupt vector (LSB) will be modified by the
provide context sensitive interrupt information for different events that require
attention from the processor. For example, hot-plug, Power Management and
RAS error events.
Depending on the number of Messages enabled by the processor in
Section
These bits are don’t care in IOxAPIC interrupt message data field specification.
RAS errors
Events
3.8.10.3, and
HP, PM
All
Table 3-34
Description
illustrates the breakdown.
xxxxxxxx
xxxxxxx0
xxxxxxx1
IV[7:0]
a
Intel 5000P Chipset MCH
137
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