NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 143

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:5
Bit
8
4
3
2
Attr
RW
RW
RW
RO
RO
0, 2-3
0
74h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
74h
Intel 5000Z Chipset
4-7
0
74h
Intel 5000P Chipset
Default
000
0h
0
0
0
ETFEN: Extended Tag Field Enable
This bit enables the PCI Express port to use an 8-bit Tag field as a requester.
The
hardwired to 0.
MPS: Max Payload Size
This field is set by configuration software for the maximum TLP payload size
for the PCI Express port. As a receiver, the Intel 5000P Chipset MCH must
handle TLPs as large as the set value. As a transmitter, it must not generate
TLPs exceeding the set value. Permissible values that can be programmed
are indicated by the Max_Payload_Size_Supported in the Device Capabilities
register:
000: 128B max payload size
001: 256B max payload size
010: 512B max payload size
011: 1024B max payload size
100: 2048B max payload size
101: 4096B max payload size
others: Reserved
Note:
programs a value that exceeds 256B for the MPS field, then it will be
considered as an error. For receive TLPs, it will be flagged as “unsupported
request” and for transmit TLPs, it will be recorded as a Malformed TLP.
Note: Due to erratum 501664, read completion coalescing cannot be used if
MPS=256 B is set by software. Read completion combining up to 128 B would
work only if the MPS is set by software. Read completion combining up to
128 B would work only if the MPS is set to 128 B. See
PEXCTRL.COALESCE_EN field.
ENRORD: Enable Relaxed Ordering
Intel 5000P Chipset MCH enforces only strict ordering only and hence this bit
is initialized to ‘0’
URREN: Unsupported Request Reporting Enable
This bit controls the reporting of unsupported requests to the
Express port.
0: Unsupported request reporting is disabled
1: Unsupported request reporting is enabled
Note that the reporting of error messages (such as ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by PCI Express port is controlled
exclusively by the PCI Express Root Control register (PEXRTCTRL) described
in
FERE: Fatal Error Reporting Enable
This bit controls the reporting of fatal errors internal to the
Express port.
0: Fatal error reporting is disabled
1: Fatal error reporting is enabled
Section
Intel 5000P Chipset MCH
The MCH supports max payload sizes only up to 256B. If Software
3.8.11.12.
does not use this field (Root complex) and is
Description
MCH
MCH
in the PCI
in the PCI
143