NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 144

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.11.5
144
PEXDEVSTS[7:2, 0] - PCI Express Device Status Register
The PCI Express Device Status register provides information about PCI Express device
specific parameters associated with this port.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:6
Bit
Bit
1
0
5
4
Attr
Attr
RO
RO
RV
RW
RW
0, 2-3
0
74h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
74h
Intel 5000Z Chipset
4-7
0
74h
Intel 5000P Chipset
0, 2-3
0
76h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
76h
Intel 5000Z Chipset
4-7
0
76h
Intel 5000P Chipset
Default
Default
000h
0h
0
0
0
Reserved.
TP: Transactions Pending
1: Indicates that the PCI Express port has issued Non-Posted Requests which
have not been completed.
0: A device reports this bit cleared only when all Completions for any
outstanding Non-Posted Requests have been received.
Since the MCH Root port that do not issue Non-Posted Requests on their own
behalf, it is hardwired to 0b.
APD: AUX Power Detected
1- AUX power is detected by the PCI Express port.
0: No AUX power is detected
NFERE: Non Fatal Error Reporting Enable
This bit controls the reporting of non fatal errors internal to the
Express port.
0: Non Fatal error reporting is disabled
1: Non Fatal error reporting is enabled
CERE: Correctable Error Reporting Enable
This bit controls the reporting of correctable errors internal to the
PCI Express port.
0: Correctable error reporting is disabled
1: Correctable Fatal error reporting is enabled
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description
MCH
MCH
in the PCI
in the