NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 156

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Figure 3-5.
156
PCI Express Hot-Plug Interrupt Flow
HPGPEEN
1
0
0
0
0
PEXSLOTCTRL[x].
PEXCMD[x].INTx
(HPGPEEN == 1)
HPINTEN = 1?
MSIEN == 1) ?
Disable == 1?
(MSICTRL[x].
PEXHPINT
N
Y
N
Y
HPINTEN
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
1
1
1
0
x
Y
Y
N
N
Intel® 5000P Chipset
Sends assert_INTx
message via DMI
Sends MSI per MSIAR
And MSIDR
per INTP
Intel® 5000P Chipset
Sends assert_HPGPE
message via DMI
Intel® 5000P Chipset
MSIEN
SW polls
status
x
1
0
0
x
INTx Disable
Intel® 5000P Chipset
Sends desassert_INTx
cleared (wired-OR)
PEXSLOTSTS str
Intel® 5000P Chipset
Sends desassert_HPGP
message via DMI
DMI when the
respective bits of
when the respective bits
PEXSLOTSTS str
E message via
cleared (wired-
when the
0
1
x
x
x
OR)
Register Description
assert_hpgpe
assert_intx
Output
MSI
--
--

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