NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 157

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.11.12
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PEXRTCTRL[7:2, 0] - PCI Express Root Control Register
The PCI Express Root Control register specifies parameters specific to the root
complex port.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:4
Bit
3
2
1
0
Attr
RW
RW
RW
RW
RV
0, 2-3
0
88h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
88h
Intel 5000Z Chipset
4-7
0
88h
Intel 5000P Chipset
Default
0h
0h
0h
0h
0h
Reserved.
PMEINTEN: PME Interrupt Enable
This field controls the generation of interrupts for PME messages.
1: Enables interrupt generation upon receipt of a PME message as reflected in
the PME Status bit defined in the PEXRTSTS register. A PME interrupt is
generated if the PMESTATUS register bit defined in
when this bit is set from a cleared state.
0: Disables interrupt generation for PME messages.
SEFEEN: System Error on Fatal Error Enable
This field controls generation of system errors in the PCI Express port
hierarchy for fatal errors.
1: Indicates that a System Error should be generated if a fatal error
(ERR_FATAL) is reported by any of the devices in the hierarchy associated
with and including this PCI Express port.
0: No System Error should be generated on a fatal error (ERR_FATAL)
reported by any of the devices in the hierarchy.
SENFEEN: System Error on Non-Fatal Error Enable
This field controls generation of system errors in the PCI Express port
hierarchy for non-fatal errors.
1: Indicates that a System Error should be generated if a non-fatal error
(ERR_NONFATAL) is reported by any of the devices in the hierarchy
associated with and including this PCI Express port.
0: No System Error should be generated on a non-fatal error
(ERR_NONFATAL) reported by any of the devices in the hierarchy.
SECEEN: System Error on Correctable Error Enable
This field controls generation of system errors in the PCI Express port
hierarchy for correctable errors.
1: Indicates that a System Error should be generated if a correctable error
(ERR_COR) is reported by any of the devices in the hierarchy associated with
and including this PCI Express port
0: No System Error should be generated on a correctable error (ERR_COR)
reported by any of the devices in the hierarchy associated with and including
this PCI Express port.
Description
Section 3.8.11.13
, is set
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