NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 16

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
16
Channel
Character
Chipset Core
Coherent
Command
Completion
Core
CRC
Critical Word First
DDR
Deasserted
Deferred
Transaction
Delayed
Transaction
DFx (DFD, DFM,
DFT, DFV)
DIMM
DIMM Rank
Double-Sided
DIMM
Downstream
DRAM Page (Row)
Dword
ECC
Intel® 631xESB/
632xESB I/O
Controller Hub
FB-DIMM
FB-DIMM Channel
FSB
Terminology
In the MCH a FB-DIMM DRAM channel is the set of signals that connects to one set of FB-
DIMM. The MCH has up to four DRAM channels.
The raw data byte in an encoded system (e.g. the 8 b value in a 8 b/10 b encoding
scheme). This is the meaningful quantum of information to be transmitted or that is
received across an encoded transmission path.
The MCH internal base logic.
Transactions that ensure that the processor's view of memory through the cache is
consistent with that obtained through the I/O subsystem.
The distinct phases, cycles, or packets that make up a transaction. Requests and
completions are referred to generically as Commands.
A packet, phase, or cycle used to terminate a transaction on a interface, or within a
component. A Completion will consistently refer to a preceding request and may or may
not include data and/or other information.
The internal base logic in the MCH.
Cyclic Redundancy Check; A number derived from, and stored or transmitted with, a block
of data in order to detect corruption. By recalculating the CRC and comparing it to the
value originally transmitted, the receiver can detect some types of transmission errors.
On the DRAM, Processor, and Memory interfaces, the requestor may specify a particular
word to be delivered first. This is done using address bits of lower significance than those
required to specify the cache line to be accessed. The remaining data is then returned in a
standardized specified order.
Double Data Rate SDRAM. DDR describes the type of DRAMs that transfers two data items
per clock on each pin. This is the only type of DRAM supported by the MCH.
Signal is set to a level that represents logical false.
A processor bus split transaction. On the processor bus, the requesting agent receives a
deferred response which allows other transactions to occur on the bus. Later, the
response agent completes the original request with a separate deferred reply transaction
or by a deferred phase.
A transaction where the target retries an initial request, but without notification to the
initiator, forwards or services the request on behalf of the initiator and stores the
completion or the result of the request. The original initiator subsequently re-issues the
request and receives the stored completion
DFD=Design for Debug
DFM=Design for Manufacturing
DFT=Design for Testability
DFV=Design for Validation
Dual-in-Line Memory Module. A packaging arrangement of memory devices on a
socketable substrate.
That set of SDRAMs on one branch which provides the data packet
Terminology often used to describe a DIMM that contain two DRAM rows. Generally a
Double-sided DIMM contains two rows, with the exception noted above. This terminology
is not used within this document.
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound”
The DRAM cells selected by the Row Address.
A reference to 32 bits of data on a naturally aligned four-byte boundary (i.e. the least
significant two bits of the address are 00b).
Error Correcting Code
Enterprise South Bridge 2.
Fully Buffered DDR2
One electrical interface to one or more Fully Buffered DDR2 DIMM.
Processor Front-Side Bus. This is the bus that connects the processor to the MCH.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Introduction

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