NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 162

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.12.4
162
UNCERRMSK[7:2] - Uncorrectable Error Mask
This register masks uncorrectable errors from the UNCERRSTS[2:7] register from being
signaled.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:21
11:6
11:6
3:1
3:1
Bit
Bit
20
19
18
17
16
15
14
13
12
5
4
0
5
4
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWCST
RWCST
Attr
RWST
RV
RV
RV
RV
Attr
0
0
104h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
RV
RV
2-3
0
108h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
108h
Intel 5000Z Chipset
4-7
0
108h
Intel 5000P Chipset
Default
Default
000
0h
0h
0
0
0
0
0
0
0
0
0
0
0
0
0h
0h
0
0
0
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Reserved
IO2Msk: Received an Unsupported Request
Reserved
IO9Msk: Malformed TLP Status
IO10Msk: Receiver Buffer Overflow Mask
IO8Msk: Unexpected Completion Mask
IO7Msk: Completer Abort Status
IO6Msk: Completion Time-out Mask
IO5Msk: Flow Control Protocol Error Mask
IO4Msk: Poisoned TLP Mask
Reserved
IO19Msk: Surprise Link Down Error Mask
IO0Msk: Data Link Layer Protocol Error Mask
Reserved
IO3Msk:Training Error Mask
Note:
Reserved
IOErr: Surprise Link Down Error Status
IO0Err: Data Link Protocol Error Status
Reserved
IO3Err:Training Error Status
Note:
This field should not be used for setting Training error Mask due to
a recent PCI-Express Base Specification, Revision 1.0a Errata Dec
2003 to remove training error. Hardware behavior is undefined.
This field should not be used for obtaining Training error status
due to a recent PCI-Express Base Specification, Revision 1.0a
Errata Dec 2003 to remove training error. Hardware behavior is
undefined.
Description
Description
Register Description