NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 167

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.12.11
3.8.12.12
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
HDRLOG0[7:2, 0] - Header Log 0
This register contains the first 32 bits of the header log locked down when the first
uncorrectable error occurs. Headers of the subsequent errors are not logged.
HDRLOG1[7:2, 0] - Header Log 1
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
This register contains the second 32 bits of the header log.
31:9
31:0
4:0
Bit
Bit
8
7
6
5
ROST
ROST
Attr
Attr
RO
RO
RO
RO
RV
0, 2-3
0
118h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
118h
Intel 5000Z Chipset
4-7
0
118h
Intel 5000P Chipset
0, 2-3
0
11Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
11Ch
Intel 5000Z Chipset
4-7
0
11Ch
Intel 5000P Chipset
Default
Default
0h
0h
0h
0
0
0
0
Reserved
ECRCCHKEN: ECRC Check Enable
This bit when set enables ECRC checking.
ECRCCHKCAP: ECRC Check Capable
Intel 5000P Chipset MCH
ECRCGENEN: ECRC Generation Enable
Intel 5000P Chipset MCH
ECRCGENCAP: ECRC Generation Capable
Intel 5000P Chipset MCH
FERRPTR: First error pointer
The First Error Pointer is a read-only register that identifies the bit position
of the first error reported in the Uncorrectable Error status register. Left
most error bit if multiple bits occurred simultaneously.
HDRLOGDW0: Header of TLP (DWORD 0) associated with first
uncorrectable error
does not support ECRC.
does not generate ECRC.
does not generate ECRC.
Description
Description
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