NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 174

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.12.22
174
EMASK_COR_PEX[7:2, 0] - Correctable Error Detect Mask
detected. But software can choose to disable detecting any of the error bits.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
This register masks (blocks) the detection of the selected bits. Normally all are
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:13
11:6
11:9
3:1
5:1
Bit
Bit
15
14
13
12
12
5
4
0
8
7
6
Attr
RW
RW
RW
RW
RW
RW
RW
RV
RV
Attr
RW
RW
RW
RW
RV
RV
RV
2-3
0
148h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
148h
Intel 5000Z Chipset
4-7
0
148h
Intel 5000P Chipset
0, 2-3
0
14Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
14Ch
Intel 5000Z Chipset
4-7
0
14Ch
Intel 5000P Chipset
Default
Default
0h
0h
0
0
0
0
0
0
0
0h
0h
0h
0
0
0
0
IO7DetMsk: Completer Abort Status
IO6DetMsk: Completion Time-out Status
IO5DetMsk: Flow Control Protocol Error Status
IO4DetMsk: Poisoned TLP Status
Reserved
IO19DetMsk: Surprise Link Down Mask
IO0DetMsk: Data Link Protocol Error Status
Reserved
IO3DetMsk:Training Error Status
This field should not be used for setting Training error severity due to a recent
PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware behavior is
undefined.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Reserved
IO16DetMsk: Replay Timer Time-out Mask
Reserved
IO15DetMsk: Replay_Num Rollover Mask
IO14DetMsk: Bad DLLP Mask
IO13DetMsk: Bad TLP Mask
Reserved
Description
Description
Register Description