NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 175

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.12.23
3.8.12.24
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
EMASK_RP_PEX[7:2, 0] - Root Port Error Detect Mask
port errors. Normally, all are detected.
PEX_FAT_FERR[7:2, 0] - PCI Express First Fatal Error Register
This register records the occurrence of the first unmasked PCI Express FATAL errors
and written by the MCH if the respective bits are not set prior. The classification of
uncorrectable errors into FATAL is based on the severity level of the UNCERRSEV
register described in
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
This register masks (blocks) the detection of the selected bits associated with the root
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:3
Bit
Bit
0
2
1
0
Attr
RW
RW
RW
Attr
RV
RW
0, 2-3
0
14Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
14Ch
Intel 5000Z Chipset
4-7
0
14Ch
Intel 5000P Chipset
0, 2-3
0
150h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
150h
Intel 5000Z Chipset
4-7
0
150h
Intel 5000P Chipset
Default
Default
0h
0
0
0
0
Section
Reserved
IO1DetMsk: Fatal Message Detect Mask
IO11DetMsk: Uncorrectable Message Detect Mask
IO17DetMsk: Correctable Message Detect Mask
IO12DetMsk: Receiver Error Mask
3.8.12.7.
Description
Description
175