NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 18

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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MCH
Mem
Memory Issue
Mesochronous
Metastability
Mirroring
MMIO
MMCFG
MSb
MSB
MTBF
Non-Coherent
Outbound
Outgoing
Packet
Page Hit.
Page Miss (Empty
Page)
Page Replace Aka
Page Miss, Row Hit/
Page Miss.
PCI
PCI 2.3 compliant
Peer to Peer
Plesiochronous
Posted
Primary PCI
Push Model
Queue
Terminology
The Memory Controller Hub component that contains the processor interface, DRAM
controller, PCI Express interface, and AGP interface. It communicates with the I/O
controller hub (Intel 631xESB/632xESB I/O Controller Hub) over a proprietary
interconnect called the Enterprise Southbridge Interface (ESI).
Used as a qualifier for transactions that target memory space. (for example, a Mem read
to I/O).
Committing a request to DDR or, in the case of a read, returning the read header.
Distributed or common referenced clock
A characteristic of flip flops that describes the state where the output becomes non-
deterministic. Most commonly caused by a setup or hold time violation.
Memory Mapped I/O. Any memory access to PCI Express.
Memory Mapped Configuration. A memory transaction that accesses configuration space.
Most Significant Bit
Most Significant Byte
Mean Time Between Failure
Transactions that may cause the processor's view of memory through the cache to be
different with that obtained through the I/O subsystem.
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound”
A transaction or completion that exits the MCH. Peer to Peer Transactions that occur
between two devices below the PCI Express or ESI ports.
The indivisible unit of data transfer and routing, consisting of a header, data, and CRC.
An access to an open page, or DRAM row. The data can be supplied from the sense amps
at low latency.
An access to a page that is not buffered in sense amps and must be fetched from DRAM
array. Address Bit Permuting Address bits are distributed among channel selects, DRAM
selects, bank selects to so that a linear address stream accesses these resources in a
certain sequence.
An access to a row that has another page open. The page must be transferred back from
the sense amps to the array, and the bank must be precharged.
Peripheral Component Interconnect Local Bus. A 32-bit or 64-bit bus with multiplexed
address and data lines that is primarily intended for use as an interconnect mechanism
within a system between processor/memory and peripheral components or add-in cards.
Refers to compliance to the PCI Local Bus Specification, Revision 2.3
Transactions that occur between two devices below the PCI Express or DMI ports.
Each end of a link uses an independent clock reference. Support of this operational mode
places restrictions on the absolute frequency difference, as specified by PCI Express,
which can be tolerated between the two independent clock references.
A transaction that is considered complete by the initiating agent or source before it
actually completes at the target of the request or destination. All agents or devices
handling the request on behalf of the original Initiator must then treat the transaction as
being system visible from the initiating interface all the way to the final destination.
Commonly refers to memory writes.
The physical PCI bus that is driven directly by the Intel 631xESB/632xESB I/O Controller
Hub component. Communication between PCI and the MCH occurs over ESI. Note that
even though the Primary PCI bus is referred to as PCI it is not PCI Bus 0 from a
configuration standpoint.
Method of messaging or data transfer that predominately uses writes instead of reads.
A storage structure for information. Anything that enters a queue will exit eventually. The
most common policy to select an entry to read from the queue is FIFO (First In First Out).
RAID-1. Please see RAID for detail descriptions.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Introduction