NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 19

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Introduction
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
RAID
RASUM
Receiver, Rcvr
Request
Reserved
RMW
Row
Row Address
Scalable Bus
SDDC
SDR
SDRAM
SEC/DED
Terminology
Redundant Array of Independent Disks. RAID improves performance by disk striping,
which interleaves bytes or groups of bytes across multiple drives, so more than one disk is
reading and writing simultaneously. Fault tolerance is achieved by mirroring or parity.
Mirroring is 100% duplication of the data on two drives (RAID-1), and parity is used
(RAID-3 and 5) to calculate the data in two drives and store the results on a third: a bit
from drive 1 is XOR'd with a bit from drive 2, and the result bit is stored on drive 3 (see
OR for an explanation of XOR). A failed drive can be swapped with a new one, and the
RAID controller automatically rebuilds the lost data. RAID can be classified into the
following categories:
RAID-0
RAID-1
RAID-2
RAID-3
RAID-4
RAID-5
RAID-6
RAID-10
Memory mirroring scheme is actually memory-RAID-1.
Reliability, Availability, Serviceability, Usability, and Manageability, which are all important
characteristics of servers.
1.
2.
component.
The contents or undefined states or information are not defined at this time. Using any
reserved area is not permitted.
Read-Modify-Write operation
A group of DRAM chips that fill out the data bus width of the system and are accessed in
parallel by each DRAM command.
The row address is presented to the DRAMs during an activate command, and indicates
which page to open within the specified bank (the bank number is presented also).
Processor-to-MCH interface. The compatible mode of the Scalable Bus is the P6 Bus. The
enhanced mode of the Scalable Bus is the P6 Bus plus enhancements primarily consisting
of source synchronous transfers for address and data, and FSB interrupt delivery. The
Intel
Single Device Disable Code; aka x4 or x8 chip-disable Hamming code to protect single
DRAM device (x4 or x8 data width) failure.
Single Data Rate SDRAM.
Synchronous Dynamic Random Access Memory.
Single-bit Error Correct / Double-symbol Error Detect
A packet, phase, or cycle used to initiate a transaction on a interface, or within a
• RAID-0 is disk striping only, which interleaves data across multiple disks for better
• Uses disk mirroring, which provides 100% duplication of data. Offers highest
• Bits (rather than bytes or groups of bytes) are interleaved across multiple disks. The
• Data are striped across three or more drives. Used to achieve the highest data
• Similar to RAID-3, but manages disks independently rather than in unison. Not often
• Most widely used. Data are striped across three or more drives for performance, and
• Highest reliability, but not widely used. Similar to RAID-5, but does two different
• Actually RAID-1,0. A combination of RAID-1 and RAID-0 (mirroring and striping).
performance. It does not provide safeguards against failure.
reliability, but doubles storage cost.
Connection Machine used this technique, but this is a rare method.
transfer, because all drives operate in parallel. Parity bits are stored on separate,
dedicated drives.
used.
parity bits are used for fault tolerance. The parity bits from two drives are stored on a
third drive.
parity computations or the same computation on overlapping subsets of the data.
Above definitions can be extended to DRAM memory system as well. To avoid
confusion, the RAID scheme for memory is referred as memory-RAID.
®
The Agent that receives a packet across an interface regardless of whether it is the
ultimate destination of the packet.
More narrowly, the circuitry required to convert incoming signals from the physical
medium to more perceptible forms.
Pentium
®
4 processor implements a subset of the enhanced mode.
Description
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