NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 191

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.13.24
3.8.13.25
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
ERR1_INT - Internal Error 1 Mask Register
This register enables the signaling of Err[1] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
ERR0_INT - Internal Error 0 Mask Register
This register enables the signaling of Err[0] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Bit
Bit
Bit
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
Attr
16
2
D2h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
2
D1h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
2
D0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B2Err2Msk: Multi-Tag Hit SF
B1Err2Msk: DM Parity Error
B8Err1Msk: SF Coherency Error for BIL
B7Err1Msk: Multiple ECC error in any of the ways during SF lookup
B6Err1Msk: Single ECC error on SF lookup
B5Err1Msk: Address Map Error
B4Err1Msk: SMBus Virtual Pin Error
B3Err1Msk: Coherency Violation Error
B2Err1Msk: Multi-Tag Hit SF
B1Err1Msk: DM Parity Error
B8Err0Msk: SF Coherency Error for BIL
B7Err0Msk: Multiple ECC error in any of the ways during SF lookup
B6Err0Msk: Single ECC error on SF lookup
B5Err0Msk: Address Map Error
B4Err0Msk: SMBus Virtual Pin Error
B3Err0Msk: Coherency Violation Error for EWB
B2Err0Msk: Multi-Tag Hit SF
B1Err0Msk: DM Parity Error
Description
Description
Description
191