NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 192

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.13.26
3.9
3.9.1
192
MCERR_INT - Internal MCERR Mask Register
This register enables the signaling of MCERR when an error flag is set. Note that one
and only one error signal should be enabled
should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and MCERR_INT for each of
the corresponding bits.
Memory Control Registers
MC - Memory Control Settings
Miscellaneous controls not implemented in other registers.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
28:25
24:22
Bit
31
30
29
21
Bit
7
6
5
4
3
2
1
0
Attr
RW
RW
RW
RV
RV
RV
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
16
2
D3h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
1
40h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
0h
0
0
0
0
0
Default
1
1
1
1
1
1
1
1
Reserved
RETRY: Retry Enable
‘1’ = enables retry.
‘0’ = disables retry.
Reserved
BADRAMTH: BADRAM Threshold
Number of consecutive instances of adjacent symbol errors required to mark a bad
device in a rank. Number of patrol scrub cycles required to decrement a non-
saturated BADCNT.
If Software desires to enable the “enhanced mode” and use the BADRAMTH, it
needs to set a non-zero value to this register field prior. Otherwise, a value of 0 is
considered illegal and memory RAS operations may lead to indeterministic
behavior.
Reserved
INITDONE: Initialization Complete. This scratch bit communicates software
state from Intel 5000P Chipset MCH to BIOS. BIOS sets this bit to 1 after
initialization of the DRAM memory array is complete. This bit has no effect on Intel
5000P Chipset MCH operation.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
B8McErrMsk: SF Coherency Error for BIL
B7McErrMsk: Multiple ECC error in any of the ways during SF lookup
B6McErrMsk: Single ECC error on SF lookup
B5McErrMsk: Address Map Error
B4McErrMsk: SMBus Virtual Pin Error
B3McErrMsk: Coherency Violation Error for EWB
B2McErrMsk: Multi-Tag Hit SF
B1McErrMsk: DM Parity Error
.
Note that one and only one error signal
Description
Description
Register Description