NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 193

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Device:
Function:
Offset:
Version:
19:18
15:9
Bit
20
17
16
8
7
6
Attr
RW
RW
RW
RW
RW
RW
RW
RV
16
1
40h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
0h
0h
0
0
0
0
0
0
FSMEN: FSM enable.
‘1’ = Enables operation of DDR protocol. This can be used as a synchronous reset to
the FSM. (normal)
‘0’ = Inhibits processing of enqueued transactions. Disables all DRAM accesses
which means that the FB-DIMM link comes up, trains, goes to L0, sends NOPs, does
alerts, syncs, fast resets, AMB configurations, and so forth, but does not perform:
a) Memory reads
b) Memory writes
c) Refreshes
Not preserved by SAVCFG bit in the SYRE register.
ETHROT: DIMM Electrical Throttling Limit
Electrical throttling is required to prevent data corruption by limiting the number of
activates within a specific time interval and is enabled by MTR.ETHROTTLE register
bit.
For each rank in the DIMM, Maximum number of activates is four per sliding
electrical throttle window as defined below:
The Memory controller should stop sending more than 4 activates for each sliding
electrical throttle window. When the sliding window boundary crosses, the counter
is reset and the process repeats.
GTW_MODE: Global Throttling window mode
This register field is used to reduce the Global throttling window size for the
purposes of debug/validation.
0: Global/open-loop throttling window of 16384*1344 (default, normal working
mode). If global throttling is enabled in this normal window, it will be held active for
16 global throttling windows without any DIMM exceeding GBLACT.
1: Global/open-loop throttling window of 4*1344 (debug, validation). If global
throttling is enabled in this debug window, it will be held active for 2 global
throttling windows without any DIMM exceeding GBLACT.
MIRROR: Mirror mode enable
‘1’ = mirroring enabled
‘0’ = mirroring disabled.
FBDHPC.NEXTSTATE defines other characteristics of mirrored mode. The Intel
5000P Chipset MCH does not support mirroring while sparing is enabled: this bit
should not be set if SPCPC.SPAREN is set. The Intel 5000P Chipset MCH does not
support mirroring with demand scrub: this bit should not be set if DEMSEN is set.
Note: When MIRROR mode is enabled, both WAY0 and WAY1 of MIR register should
be set to 1. Otherwise, it is a programming error.
Reserved
SCRBALGO: Scrub Algorithm for x8 uncorrectable error detection
0: Normal mode
1: Enhanced mode
SCRBEN: Patrol Scrub Enable
1: Enables patrol scrubbing.
0: Disables patrol scrubbing
The scrub engine will start the scrub operations from the beginning to the end of
the memory each time the SCRBEN register bit is set.
Note that SCRBEN should be disabled during MIR updates.
DEMSEN: Demand Scrub Enable
Enables demand scrubbing. This bit must not be set when MIRROR is set.
00: 10 clocks(DDR533)
01: 13 clocks(DDR667)
10: 15 clocks(DDR800)
11: 20 clocks(safe/conservative setting)
Description
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