NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 194

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.2
Table 3-37. Global Activation Throttling as a Function of Global Activation Throttling Limit
194
GBLACT - Global Activation Throttle Register
This register contains the hostel limit for Global Activation throttle control.
a. If (MC.GTW_MODE==1), then the global throttling window is 4*1344 cycles (debug, validation). Else if
(GBLACTM) and Global Throttling Window Mode (GTW_MODE) Register Fields
Notes:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
3:0
7:0
Bit
Bit
(MC.GTW_MODE==0), then the window is set to 16384*1344 cycles (normal).
5
4
GBLACT.GBLACTM
Range (0.168)
RWC
Attr
Attr
RW
RW
RV
16
32
64
0
1
2
16
1
40h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
1
60h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
0h
0
0
0
ERRDETEN: Error Detection Enable
‘1’ = Northbound CRC/ECC checking enabled.
‘0’ = Northbound CRC/ECC checking disabled
FB-DIMM “Alert” detection is disabled, status packets are ignored, northbound error
logging and data poisoning are disabled when Northbound CRC/ECC checking is
disabled.
SCRBDONE: Scrub Complete
The scrub unit will set this bit to ‘1’ when it has completed scrubbing the entire
memory. Software should poll this bit after setting the Scrub Enable (SCRBEN) bit
to determine when the operation has completed. If the Scrub enable bit is cleared
midway during the scrub cycle, then the SCRBDONE bit will not be set and the Intel
5000P Chipset MCH will stop the scrub cycle immediately.
Reserved
GBLACTLM: Global Activation Throttle Limit
This field controls the activation of Global throttling based on the number of
activates sampled per DIMM pair on each branch.
If the number of activates in the global throttling window
indicated by the GBLACTLM filed in this register, then global throttling is started by
setting the THRSTS[1:0].GBLTHRT bit for the respective branch and the Global
activation throttling logic to use the THRTMID register for throttling.
The granularity of this field is 65536 activations. Refer to
If Software sets this value greater than 168, the chipset will cap the GBLACTLM
field to 168.
(16384*1344 window)
(unlimited activations)
MC.GTW_MODE=0
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
No Throttling
1048576
2097152
4194304
131072
65536
Number of Activations
(unlimited activations)
MC.GTW_MODE=1
(4*1344 window)
Description
Description
No Throttling
1024
256
512
16
32
a
Table 3-37
exceeds the number
Register Description