NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 198

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.9
3.9.10
198
DDRFRQ - DDR Frequency Ratio
This register specifies the CORE:DDR frequency ratio.
FBDTOHOSTGRCFG0: FB-DIMM to Host Gear Ratio
Configuration 0
This register consists of 8 nibbles of mux select data for the proper selection of gearing
behavior on the FB-DIMM. This is the first of two registers to control the behavior for
the FB-DIMM to host (north bound) data flow.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
13:0
7:6
5:4
3:2
1:0
Bit
Bit
14
RWST
Attr
Attr
RW
RO
RV
RV
RV
16
1
58h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
1
56h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
0000h
00h
00h
0h
00
0
SCHDIMM: Single Channel DIMM Operation
0: The MC assumes that the Intel 5000P Chipset MCH is operating normally, that is,
MC is not operating with only one FB-DIMM channel as in single channel mode.
1: In this mode, the Intel 5000P Chipset MCH MC will operate such that only 1
channel (that is, branch 0, channel 0) is active and there can be one or more
DIMMS present in Channel 0.
Reserved.
Reserved1
NOW: Present CORE:DDR Frequency Ratio
‘00’ = 1:1. for example, if BUSCLK=333 MHz, then DDR=667 MHz.
‘01’ = Reserved
‘10’ = 4:5. for example, if BUSCLK=266 MHz, then DDR=667 MHz.
‘11’ = 5:4. for example, if BUSCLK=333 MHz, then DDR=533 MHz.
This field will only specify the relationship between the CORE-domain and FB-
DIMM-domain clocks. This field does not indicate the frequency of the FB-DIMM
SCiD link... that is entirely determined by the frequency of the FBDCLK reference
clocks. To achieve successful FB-DIMM channel initialization, the frequency of the
FBDCLK reference clock must match the frequency of the FB-DIMM-domain clock.
E.g. if the BUSCLK=333 MHz and the NOW field specifies a ratio of 1:1, then
FB-DIMM channel initialization will succeed with an FBDCLK frequency of 333 MHz.
Reserved
NEXT: Future CORE:DDR Frequency Ratio
This frequency ratio will take effect and transfer to the “NOW” field after the next
Intel 5000P Chipset MCH hard reset.
‘00’ = 1:1. for example, if BUSCLK=333 MHz, then DDR=667 MHz.
‘01’ = Reserved
‘10’ = 4:5. for example, if BUSCLK=266 MHz, then DDR=667 MHz.
‘11’ = 5:4. for example, if BUSCLK=333 MHz, then DDR=533 MHz.
This field will only set the relationship between the CORE-domain and FB-DIMM-
domain clocks. This field will not set the frequency of the FB-DIMM SCiD link... that
is entirely determined by the frequency of the FBDCLK reference clocks. To achieve
successful FB-DIMM channel initialization, the frequency of the FBDCLK reference
clock must match the frequency of the FB-DIMM-domain clock. For example, if the
BUSCLK=333 MHz and the NEXT field specifies a ratio of 1:1, then after the next
Intel 5000P Chipset MCH hard reset, FB-DIMM channel initialization will succeed
with an FBDCLK frequency of 333 MHz.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description