NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 21

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Introduction
1.2
Table 1-1.
1.2.1
1.3
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Related Documents and Materials
Related Documents
BIOS Self-test Utility
The BIOS self test utility for the MCH is available from your Intel field representative.
The following password is required to unzip this tool.
The password for this chipset is (case sensitive): zxcv+_)(
Intel 5000P Chipset Overview
Figure 1-1
The Intel 5000P chipset is designed for use in server systems based on the processor
Dual-Core Intel Xeon 5000 Sequence processor. The Intel 5000P chipset supports two
processors on dual independent point to point system buses operating at 266 MHz
(1066 MTS) or two processors on dual independent point to point system buses
operating at 333 MHz (1333 MTS). The theoretical bandwidth of the two processor
busses is 17 GB/s for Dual-Core Intel Xeon 5000 series and 21 GB/s for for Dual-Core
Intel Xeon 5100 series. The MCH supports 36 bit addressability for a total 64 GB of
physical memory.
The Dual-Core Intel Xeon 5000 Series has a 2 MB L2 cache, a 266 MHz (1066 MTS)
system bus and Dual-Core Intel Xeon 5100 Series has a 4 MB shared L2 cache, a
333 MHz (1333 MTS) system bus. They are fabricated using a 65nm process in a
771-pin LGA package.
In the Intel 5000P chipset-based platform, the MCH provides the processor interface,
fully buffered DIMM memory interfaces, PCI Express* bus interfaces, ESI interface, and
SM Bus interfaces.
The MCH provides four channels of Fully Buffered DIMM (FB-DIMM) memory. Each
channel can support up to 4 Dual Ranked FB-DIMM DDR2 DIMMs. FB-DIMM memory
channels are organized in to two branches for support of RAID 1 (mirroring). The MCH
can support up to 16 DIMMs or a maximum memory size of 64 GB physical memory in
non-mirrored mode and 32 GB physical memory in mirrored configuration. The read
bandwidth for each FB-DIMM channel is 4.25 GB/s for DDR2 533 FB-DIMM memory
Guide
Dual-Core Intel
Mechanical Design Guideline
Intel
Design Specification
Intel
Dual-Core Intel
Mechanical, and Thermal Specifications (EMTS).
Intel
JEDEC FB-DIMM Memory Specification
PCI Local Bus Specification, Rev 2.3.
PCI Express Interface Specification, Rev 1.0a
Digital Visual Interface (DVI) Specification, Rev 1.0
Dual-Core Intel
®
®
®
6402/6400 Advanced Memory Buffer Component External
631xESB/632xESB I/O Controller Hub Datasheet
5000 Series Chipsets MCH BIOS Specification
shows an example block diagram of a Intel 5000P chipset-based platform.
®
®
®
Xeon
Xeon
Xeon
®
®
®
Processor 5000 Sequence Thermal/
Processor 5000 Sequence Electrical,
Processor-Based Servers Platform Design
Document
http://developer.intel.com/design/
http://developer.intel.com/design/
http://developer.intel.com/design/
http://developer.intel.com/design/
http://developer.intel.com/design
www.jedec.org
www.pcisig.org
www.pcisig.org
http://www.ddwg.org/downloads.html
http://developer.intel.com/design
Document Number/ Location
21