NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 217

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Register Description
3.9.22.10
3.9.22.11
3.9.22.12
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
NRECMEMA - Non-Recoverable Memory Error Log Register A
This register latches information on the first detected fatal memory error.
NRECMEMB - Non-Recoverable Memory Error Log Register B
This register latches information on the first detected fatal memory error.
NRECFGLOG - Non-Recoverable DIMM Configuration Access Error Log
Register
This register latches information on the first detected non-fatal DIMM configuration
register access.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
14:12
31:28
27:16
31:28
27:24
23:16
15:12
10:8
14:0
10:8
7:0
7:0
Bit
Bit
Bit
15
11
15
11
ROST
ROST
ROST
ROST
ROST
ROST
ROST
ROST
ROST
ROST
ROST
Attr
Attr
Attr
RV
RV
RV
RV
RV
16
1
BEh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
1
C0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
1
C4h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
16
Default
Default
Default
000h
00h
00h
00h
0h
0h
0h
0h
0h
0h
0h
0h
0
0
0
0
Reserved
BANK: Bank of the failed request
RDWR
‘0’ = Read
‘1’ = Write
RANK: Rank of the failed request
REC_FBD_DM_BUF_ID: DM Buffer ID of the failed request
Reserved
CAS: CAS address of the failed request
Reserved
RAS: RAS address of the failed request
Reserved
BE: Byte Enables of the failed request
REG: Register Address of the failed request
Reserved
RDWR
‘0’ = Read
‘1’ = Write
FUNCTION: Function Number of the failed request
CFG_FBD_DM_BUF_ID: DM Buffer ID of the failed request
Description
Description
Description
217

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