NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 226

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 3-6.
3.9.23.5
226
FB-DIMM Reset Timing
SPCPC[1:0] - Spare Copy Control
These controls set up sparing for each branch. Branch zero (device 21) takes
precedence over branch one (device 22): if both spare-control-enabled branches’ spare
error thresholds trigger in the same cycle, sparing will only commence on branch zero.
Sparing will not commence on a competing branch until its in-progress competitor’s
spare control enable is cleared and it’s UERRCNT/CERRCNT criteria is still met.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Bit
7:
3
2
1
0
RWST
RWST
RWST
Attr
RV
SOFTCORERESET#
21
0
53h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
53h
Intel 5000P Chipset
Default
00h
0
0
0
CORERESET#
FBD PLL
FBDCLK
Reserved
BRSELCMPRESET: Branch Select for Compensation Reset
0: COMPreset is tied to CORERESET# from branch 0
1: COMPreset is tied to CORERESET# from branch 1
For Branch 1 to be selected for reset, this field has to be a ‘1’ for both branch
instances.
SOFTCORERESET#: Soft Core Reset
See Timing diagram
0: Soft Core Reset Asserted
1: Soft Core Reset De-Asserted
CORERESET#: Core Reset
See Timing diagram
0: Core Reset Asserted
1: Core Reset De-Asserted
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
UNLOCKED
Figure
Figure
ENABLED
0
T
1
3-6.
3-6.
21ns
LOCKED
Description
2us
3ns
Register Description