NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 229

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.9.23.9
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Each register defines a range. If the Memory (M) address falls in the range defined by
an adjacent pair of DMIR.LIMIT’s, the rank fields in the upper DMIR define the number
and interleave position of ranks’ way participation. Matching addresses participate in
the corresponding ways. The combination of two equal ranks with three unequal ranks
is illegal.
When a DMIR is programmed for a 2-way interleave, RANK0/RANK2 should be with the
same rank number and RANK1/RANK3 should be another rank number.
This register must not be modified while servicing memory requests.
FBDICMD[1:0][1:0] - FB-DIMM Initialization Command
These registers define channel behavior during the “Init”, “Recovery Init”, “Reset”, and
“Recovery Reset” hot-plug states. The “AMBID” field for the even-numbered channel
also defines branch behavior during fast reset.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:24
23:16
15:12
11:9
8:6
5:3
2:0
Bit
Bit
7
Attr
Attr
RW
RW
RW
RW
RW
RW
RV
RV
21
0
A0h, 9Ch, 98h, 94h, 90h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
A0h, 9Ch, 98h, 94h, 90h
Intel 5000P Chipset
21
0
47h, 46h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
47h, 46h
Intel 5000P Chipset
Default
Default
000h
00h
000
000
000
000
0h
0
Reserved
LIMIT
This field defines the highest address in the range. Memory requests
participate in this DMIR range if LIMIT[i] > M[34:28] >= LIMIT[i-1]. For i = 0,
LIMIT[i-1]=0 (M[35] is considered as zero for the purpose of this comparison).
Reserved
RANK3
Defines which rank participates in WAY3.
RANK2
Defines which rank participates in WAY2.
RANK1
Defines which rank participates in WAY1.
RANK0
Defines which rank participates in WAY0.
EN: Enable
This field is not used during fast reset.
‘0’ = Drive electrical idle on the channel.
‘1’ = Drive INITPAT on the channel.
Description
Description
229