NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 232

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.24
3.9.24.1
Note:
3.9.24.2
Note:
232
FB-DIMM RAS Registers
There are two sets of the following registers, one set for each FB-DIMM branch. They
each appear in function 0 of different devices as shown in
UERRCNT[1:0] - Uncorrectable Error Count
This register implements the “leaky-bucket” counters for uncorrectable errors for each
rank. Each field “limits” at a value of “15” (“1111”). Non-zero counts are decremented
when the ERRPER threshold is reached by the error period counter. Counts are frozen at
the threshold defined by SPCPC.SETH and set the SPCPS.LBTHR bit. Writing a value of
“1111” clears and thaws the count. Changing SPCPC.SETH has no effect upon a frozen
count.
Aliased uncorrectable errors are NOT counted as uncorrectable errors in the
implementation of this register. They are treated as correctable errors and logged in
the CERRCNT register.
CERRCNT[1:0] - Correctable Error Count
This register implements the “leaky-bucket” counters for correctable errors for each
rank. Each field “limits” at a value of “15” (“1111”). Non-zero counts are decremented
when the ERRPER threshold is reached by the error period counter. Counts are frozen at
the threshold defined by SPCPC.SETH and set the SPCPS.LBTHR bit. Writing a value of
“1111” clears and thaws the count. Changing SPCPC.SETH has no effect upon a frozen
count.
Aliased uncorrectable errors are counted as correctable errors in the implementation of
this register.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0
Bit
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
Attr
21
0
A4h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
A4h
Intel 5000P Chipset
Default
0h
0h
0h
0h
0h
0h
0h
0h
RANK7: Error Count for Rank 7
RANK6: Error Count for Rank 6
RANK5: Error Count for Rank 5
RANK4: Error Count for Rank 4
RANK3: Error Count for Rank 3
RANK2: Error Count for Rank 2
RANK1: Error Count for Rank 1
RANK0: Error Count for Rank 0
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Table
3-3.
Register Description