NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 234

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.24.5
3.9.24.6
234
BADCNT[1:0] - Bad DRAM Counter
This register implements “failing-device” counters for the aliased uncorrectable error
identification algorithm. “Count” double-adjacent symbol errors within x8 devices.
“Drip” each counter after “MC.BADRAMTH” patrol scrub cycles through all of memory.
Values of “MC.BADRAMTH” and “0” cannot be “dripped”. A value of “MC.BADRAMTH”
cannot be incremented. “Mark” the BADRAM(A/B) register when a count reaches
“MC.BADRAMTH”.
FBDSBTXCFG[1:0][1:0]: FB-DIMM Southbound Transmit Configuration
Register
This register controls the FB-DIMM Southbound I/O Transmit configuration during
normal operation. This value is programmed by BIOS on per channel basis.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:10
31:28
27:24
23:20
19:16
15:12
11:8
9:5
4:0
7:4
3:0
Bit
Bit
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
Attr
Attr
RV
21
0
B0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
B0h
Intel 5000P Chipset
21
0
B4h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
B4h
Intel 5000P Chipset
Default
Default
0000
0000
0000
0000
0000
0000
0000
0000
00h
00h
00h
Reserved
RANK7: Bad device in Rank 7
RANK6: Bad device in Rank 6
RANK7: Adjacent x8 symbol error count in Rank 7
RANK6: Adjacent x8 symbol error count in Rank 6
RANK5: Adjacent x8 symbol error count in Rank 5
RANK4: Adjacent x8 symbol error count in Rank 4
RANK3: Adjacent x8 symbol error count in Rank 3
RANK2: Adjacent x8 symbol error count in Rank 2
RANK1: Adjacent x8 symbol error count in Rank 1
RANK0: Adjacent x8 symbol error count in Rank 0
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description