NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 239

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Register Description
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Device:
Function: 0
Offset:
7:6
Bit
5
4
3
2
1
0
RWCST
RWCST
RWST
RWST
Attr
RW
RW
RW
21
280h, 180h
Default
0
1
1
0
0
1
0
ERRSTAT: Port Error Status [1:0]
When IBIST is started, status goes to 01 until first start delimiter is received and
then goes to 00 until the end or to10/11 as appropriate.
00: No error.
01: Did not receive first start delimiter.
10: Transmission error (first error).
11: Reserved.
TXAUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
the FIBTXSHFT register.
0: Disable Auto-inversion
1: Enable Auto-inversion
STOPONERR: Stop IBIST on Error
0: Do not stop on error, only update error counter
1: Stop on error
LOOPCON: Loop continuously
Enable IBIST operations to loop continuously. The IBIST pattern generator
executes the each pattern loop for the counts specified in the bit fields but the
overall loop runs continuously. This bit should be protected (gated) by the
component’s security mechanisms.
0: No continuous operation
1: Loop continuously
IBDONE: IBIST done flag
0: Not done
1: Done
MSTRMD: Master Mode Enable
When this bit is set the next TS1 training set that has the loopback bit set will
cause the transmitter to operate as a master. Even though the IBIST is in the
loopback state it is not in loopback.
0: Disable Master mode. This component will not enter into master when a TS1
training set with loopback bit set.
1: Enable Master Mode on the next TS1 training with loopback bit set
IBSTR: IBIST Start
When set, it enables receiver logic to look for start delimiters during TS1 training
set. If the MSTRMD bit is set, the start bit enables the transmit state machine to
start transmitting patterns during the TS1 training set. The receiver is enable in
both cases.
For master-slave mode, the pattern will be looped back as defined in the FB-
DIMM spec. In master-master mode, the IBIST controller will originate patterns
and also check the incoming pattern for errors.
0: Stop IBIST transmitter
1: Start IBIST transmitter
Description
239

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