NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 244

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.25.12
3.9.25.13
244
FBD[1:0]IBTXSHFT: IBIST Transmit Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
FBD[3:2]IBRXSHFT: IBIST Receive Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
31:14
13:10
31:14
13:10
31:14
9:0
9:0
Bit
Bit
Bit
RWST
RWST
RWST
RWST
Attr
Attr
Attr
RV
RV
RV
22
294h, 194h
21
294h, 194h
22
298h, 198h
Default
Default
Default
001h
001h
0h
0h
0h
0h
0h
Reserved
txinvshfthvm: Transmit Inversion shift register extra DFT pins for HVM
symmetry
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during IBIST
operations.
txinvshft: Transmitter Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during IBIST
operations.
Reserved
txinvshfthvm: Transmit Inversion shift register extra DFT pins for HVM
symmetry
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during IBIST
operations.
txinvshft: Transmitter Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during IBIST
operations.
Reserved
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Register Description