NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 246

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

246
This register enables IBIST operations for individual lanes.
Device:
Function: 0
Offset:
31:14
12:0
Bit
13
ROST
ROST
Attr
RV
21
29Ch, 19Ch
Default
0h
0
0
Reserved
rxerrstat: Receive error lane status for DFT.
This register records the error from lane 13 of this port.
rxerrstat: Receive error lane status.
This register records the errors from all lanes of this port.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Register Description