NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 249

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Register Description
3.9.25.19
3.9.25.20
3.9.25.21
3.9.25.22
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
FBD[3:2]IBPATBUF2: FB-DIMM IBIST Pattern Buffer 2 Register
This register contains the pattern bits used in IBIST operations.
FBD[1:0]IBPATBUF2: FB-DIMM IBIST Pattern Buffer 2 Register
This register contains the pattern bits used in IBIST operations.
FBD[3:2]IBTXPAT2EN: IBIST TX Pattern Buffer 2 Enable
This register enables which channels are inverted when IBIST operations are activated.
FBD[1:0]IBTXPAT2EN: IBIST TX Pattern Buffer 2 Enable
This register enables which channels are inverted when IBIST operations are activated.
Device:
Function: 0
Offset:
31:24
23:0
Device:
Function: 0
Offset:
31:24
23:0
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
31:14
13:10
31:14
9:0
Bit
Bit
Bit
Bit
RV
RWST
RV
RWST
RWST
RWST
Attr
Attr
Attr
Attr
RV
RV
22
21
22
21
2A4h, 1A4h
2A4h, 1A4h
2A8h, 1A8h
2A8h, 1A8h
0
02CCFDh
0
02CCFDh
Default
Default
Default
Default
3FFh
0h
Fh
0h
Reserved
txpatt2hvmen: receiver Pattern Buffer 2 Enable for the HVM lanes
Selects which channels to enable the second pattern buffer.
txpatt2en: receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
Reserved
Reserved
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
Reserved
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
Description
Description
Description
Description
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