NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 250

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.25.23
3.9.25.24
250
FBD[3:2]IBRXPAT2EN: IBIST RX Pattern Buffer 2 Enable
This register enables inversion pattern testing on individual lanes.
FBD[1:0]IBRXPAT2EN: IBIST RX Pattern Buffer 2 Enable
This register enables inversion pattern testing on individual lanes.
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
13:10
31:14
31:14
13:0
13:0
9:0
Bit
Bit
Bit
RWST
RWST
RWST
RWST
Attr
Attr
Attr
RV
RV
21
2A8h, 1A8h
22
2ACh, 1ACh
21
2ACh, 1ACh
Default
Default
Default
3FFFh
3FFFh
3FFh
Fh
0h
0h
txpatt2hvmen: receiver Pattern Buffer 2 Enable for the HVM lanes
Selects which channels to enable the second pattern buffer.
txpatt2en: receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
Reserved
rxpatt2en: Receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
Reserved
rxpatt2en: Receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Register Description