NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 257

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.10.8.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
1. When software initiates an S0 => S3 transition, it should make the DMA engine device to enter
D3 before completing the power management handshake with the MCH.
PMCAP - Power Management Capabilities Register
The PM Capabilities Register defines the capability ID, next pointer and other power
management related support. The following PM registers /capabilities are added for
software compliance.
Device:
Function:
Offset:
Version:
31:27
24:22
18:16
15:8
7:0
Bit
26
25
21
20
19
Attr
RO
RO
RO
RO
RO
RO
RO
RO
RO
RV
8
0
50h
Intel 5000P Chipset
Default
11001
010
58h
01h
0h
0
0
0
0
0
PMES: PME Support
Identifies power states which assert PMEOUT. Bits 31, 30 and 27 must be set
to '1' for PCI-PCI bridge structures representing ports on root complexes. The
definition of these bits is taken from the PCI Bus Power Management Interface
Specification Revision 1.1.
XXXX1b -
XXX1Xb -
Chipset MCH)
XX1XXb -
Chipset MCH)
X1XXXb -
1XXXXb -
D2S: D2 Support
The Intel 5000P Chipset MCH does not support power management state D2.
D1S: D1 Support
The Intel 5000P Chipset MCH does not support power management state D1.
AUXCUR: AUX Current
DSI: Device Specific Initialization
Reserved.
PMECLK: PME Clock
This field is hardwired to 0h.
VER: Version
This field is set to 2h as version number from the PCI Express 1.0
specification.
NXTCAPPTR: Next Capability Pointer
This field is set to offset 58h for the next capability structure (MSI) in the PCI
2.3 compatible space.
CAPID: Capability ID
Provides the PM capability ID assigned by PCI-SIG.
PMEOUT
PMEOUT
PMEOUT
PMEOUT
PMEOUT
can be asserted from D0
can be asserted from D1 (Not supported by Intel 5000P
can be asserted from D2 (Not supported by Intel 5000P
can be asserted from D3 hot
can be asserted from D3 cold
Description
257