NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 26

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Note:
Table 2-1.
Table 2-2.
26
2.6 VGPIO 2.6 V buffers used for miscellaneous GPIO signals
CMOS
Host Interface signals that perform multiple transfers per clock cycle may be marked as
either “4X” (for signals that are “quad-pumped”) or 2X (for signals that are “double-
pumped”).
Processor address and data bus signals are logically inverted signals. In other words,
the actual values are inverted of what appears on the processor bus. This must be
taken into account and the addresses and data bus signals must be inverted inside the
MCH host bridge. All processor control signals follow normal convention. A 0 indicates
an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an
active level (high voltage) if the signal has no # suffix.
Signal Naming Conventions
Table 2-2
Buffer Signal Types
RR{0/1/2}XX
RR[2:0]
RR{0/1/2}
RR# or RR[2:0]#
I
O
A
I/O
Convention
Direction
Buffer
CMOS buffers
lists the reference terminology used for signal types.
Expands to: RR0XX, RR1XX, and RR2XX. This denotes similar signals
on replicated buses.
Expands to: RR[2], RR[1], and RR[0]. This denotes a bus.
Expands to: RR2, RR1, and RR0. This denotes electrical duplicates.
Denotes an active low signal or bus.
Input signal
Output signal
Analog
Bidirectional (input/output) signal
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Expands to
Signal Description