NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 260

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Figure 3-7.
260
Intel 5000P Chipset DMA Error/Channel Completion Interrupt Handling Flow
MSIEN
1
1
0
0
MSICBEN
DMA errors/completion
1
0
x
x
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PEXCMD[x].INTx
Disable == 1?
(MSICTRL[x].
MSIEN == 1)
interrupts
Y
N
INTx Disable
N
0
1
x
x
Y
Intel® 5000P Chipset
INTRCTRL.intp is
Sends assert_INTx
Intel® 5000P Chipset
Sends deassert_INTx
per INTP when
reset (wired-OR)
message via DMI
message via DMI
per INTP
MSICBEN == 1)?
(PEXCTRL[x]
assert_intx
Output
MSI
N
--
--
Register Description
Channel completions
Y
MSI For both DMA
Will send only 1
interrupts and
MSIDR

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