NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 263

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.10.16
3.10.17
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PEXCAPS - PCI Express Capabilities Register
PEXDEVCAP - Device Capabilities Register
Device:
Function:
Offset:
Version:
15:14
13:9
8
7:4
3:0
Device:
Function:
Offset:
Version:
31:28
27:26
25:18
17:15
14
13
12
11:9
8:6
5
4:3
Bit
Bit
RV
RO
RO
RO
RO
RV
RO
RO
RV
RO
RO
RO
RO
RO
RO
RO
Attr
Attr
8
0
6Eh
Intel 5000P Chipset
8
0
70h
Intel 5000P Chipset
0h
0h
0
0000
0001
0h
00
00h
0h
0
0
0
000
000
0
00
Default
Default
Reserved
IMN: Interrupt Message Number:
This field indicates the interrupt message number that is generated from the
Engine
field is required to contain the offset between the base Message Data and the MSI
Message that is generated when the status bits in the slot status register or root port
status registers are set.
Slot_Impl: Slot Implemented: DMA Engine is an integrated device and therefore a
slot is never implemented.
DPT: Device/Port Type: DMA Engine device represents a PCI Express Endpoint.
VERS:
specification.
Reserved
CSPLS: Captured Slot Power Limit Scale
This field applies only to upstream ports.
CSPLV: Captured Slot Power Limit Value
This field applies only to upstream ports.
Reserved
PIPD: Power Indicator Present
The DMA Engine is an integrated device and therefore, an Power Indicator does not
exist.
AIPD: Attention Indicator Present
The DMA Engine is an integrated device and therefore, an Attention Indicator does
not exist.
ABPD: Attention Button Present
The DMA Engine is an integrated device and therefore, an Attention Button does not
exist.
EPL1AL: Endpoint L1 Acceptable Latency
The DMA Engine device is not implemented on a physical PCI Express link and
therefore, this value is irrelevant.
EPL0AL: Endpoint L0s Acceptable Latency
The DMA Engine device is not implemented on a physical PCI Express link and
therefore, this value is irrelevant.
ETFS: Extended Tag Field Supported
The DMA Engine device does not support extended tags.
PFS: Phantom Functions Supported
The DMA Engine device does not support Phantom Functions.
Hardwired to 0h
Hardwired to 0h
device. When there are more than one MSI interrupt Number, this register
Capability Version: DMA Engine supports Revision 1 of the PCI Express
Hardwired to 0h
Hardwired to 0h
Hardwired to 0h
Description
Description
Hardwired to 0h
Hardwired to 0h
Hardwired to 0h
Hardwired to 0h
DMA
263