NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 266

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.11
3.11.1
266
PCI Express IBIST Registers
DIOIBSTR: PCI Express IBIST Global Start/Status Register
This register contains the global start for all the ports in the Intel 5000P Chipset MCH
component simultaneously. One start bit is placed in the register for each port. IBIST
will start at approximately the same time on all ports written to with a 1 in the same
write access.
Device:
Function:
Offset:
Version:
1
0
Device:
Function:
Offset:
Version:
Bit
Bit
7
6
5
4
3
2
1
0
RWC
RWC
Attr
Attr
RW
RW
RW
RW
RW
RW
RW
RV
8
0
76h
Intel 5000P Chipset
0
0
398h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
0
0
Default
Default
0
0
0
0
0
0
0
0
NFED: Non-Fatal Error Detected
This bit gets set if a non-fatal uncorrectable error is detected.
Errors are logged in this register regardless of whether error reporting is enabled or
not in the Device Control register.
1: Non Fatal errors detected
0: No non-Fatal Errors detected
CED: Correctable Error Detected
This bit gets set if a correctable error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the
register. (See CERE in
1: correctable errors detected
0: No correctable errors detected
START7: Writing a 1 starts IBIST on port 7.
START6: Writing a 1 starts IBIST on port 6.
START5: Writing a 1 starts IBIST on port 5.
START4: Writing a 1 starts IBIST on port 4.
START3: Writing a 1 starts IBIST on port 3.
START2: Writing a 1 starts IBIST on port 2.
Reserved
START0: Writing a 1 starts IBIST on port 0.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Section 3.10.18
§
§
(See NFERE in
Description
Description
)
Section 3.10.18
Register Description
Device Control
)