NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 268

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.11.4
268
PEX[7:2,0]IBCTL: PEX IBIST Control Register
This register contains the control bits and status information necessary to operate the
Fixed and Open modes of the IBIST logic. The default settings allow the CMM logic to
operate with link width of a PEX port. Only valid PCI Express control characters/
symbols are allowed for IBIST testing.
Device:
Function: 0
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function: 0
Offset:
Version:
27:23
22:14
13:9
Bit
31
30
29
28
8
RWCST
3-2, 0
380h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
7-4
380h
Intel 5000P Chipset
Attr
RW
RW
RW
RW
RV
RO
RO
4-5
0
380h
Intel 5000Z Chipset
Default
0h
0h
0
1
0
1
0
0
SYMTYPSEL3: Symbol[3] Type Select
1: selects Symbol [3] as a control character
0: selects Symbol [3] to a data character
SYMTYPSEL2: Symbol[2] Type Select
1: selects Symbol [2] as a control character
0: selects Symbol [2] to a data character
SYMTYPSEL1: Symbol[1] Type Select
1: selects Symbol [1] as a control character
0: selects Symbol [1] to a data character
SYMTYPSEL0: Symbol[0] Type Select
1: selects Symbol [0] as a control character
0: selects Symbol [0] to a data character
Reserved
ERRVAL: Error Value
This is the raw 9-bit error value captured on the lane that asserted the Error
Detected bit (ERRDET) or the Global Error status bit if this register is
implemented. The value must be extracted in the datapath before the 10b/8b
decoder in order to examine its contents for debugging potential link errors.
ERRLNNUM: Error Lane Number
This field indicates which lane reported the error that was detected when
ERRDET was asserted.
Note: When the number of lanes reporting exceeds 32, this field will show an
aliased error lane number and cannot be used to indicate the errant lane.
Larger lane indications will require an extended register to display accurate
information.
ERRDET: Error Detected
A mis-compare between the transmitted symbol and the symbol received on
link indicates an error condition occurred. Refer to Error Value, Error Symbol
Pointer and Error Symbol Type bit fields for further information about fault
locations. This bit is cleared by writing a logic ‘1’ and it remains asserted
through reset (sticky).
0: No error detected
1: Error Detected
Note: The error signal that causes this bit to be set should be made available
externally to the IBIST logic. It is implementation specific as to how this is
accomplished. The purpose is for symbol (bit) error rate testing. It is assumed
that this signal is either sent to a performance counter or an external pin for
signal assertion accumulation. There is not any error counting resources
available in this spec.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Register Description