NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 269

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.11.5
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PEX[7:2,0]IBSYMBUF: PEX IBIST Symbol Buffer
This register contains the character symbols that are transmitted on the link. Only valid
PCI Express control characters/symbols are allowed for IBIST testing.
Device:
Function: 0
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function: 0
Offset:
Version:
6:4
Bit
7
3
2
1
0
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
7-4
3-2, 0
380h
380h
Intel 5000P Chipset
Attr
RW
RW
RW
RW
RW
RV
4-5
0
380h
Intel 5000Z Chipset
Default
000
0
1
0
0
0
SUPSKP: Suppress Skips
0: Skips are still inserted in the IBIST data stream during IBIST test
operations.
1: Skip insertion is suppressed
DSYMINJLNUM: Delay Symbol Injection Lane Number
This selects the Lane number to inject the delay symbol pattern. All 8 values
could be valid depending on the setting of the IBEXTCTL.LNMODUEN bit field.
This is true regardless of whether this IBIST engine is instantiated for a x4 or
a x8 port.
AUTOSEQEN: Automatic Sequencing Enable of Delay Symbol
0: Disable delay symbol auto-sequence. IBIST does not automatically
sequence the delay symbol across the width of the link.
1: Enable delay symbol auto-sequencing.
Reserved
INITDISP: Initial Disparity
This bit sets the disparity of the first IBIST data pattern symbol. The default is
negative meaning that the first symbol transmitted by Tx will have a negative
disparity regardless of what the running disparity is. This allows a
deterministic pattern set to be transmitted on the link for every IBIST run. If
IBIST causes a discontinuous disparity error in the receiver this error can be
ignored in the reporting register. It will not affect the operation of the IBIST
since it is outside of its domain. Higher levels of software management must
be aware that side effects from running IBIST could cause other errors and
should they be ignored.
0: Disparity starts as negative
1: Disparity starts as positive
IBSTR: IBIST Start
This bit is OR’ed with the global start bit.
0: Stop IBIST
1: Start IBIST
Description
269