NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 270

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.11.6
270
PEX[7:2,0]IBEXTCTL: PEX IBIST Extended Control
Register
This register extends the functionality of the IBIST with pattern loop counting, skip
character injection, and symbol management. A bit is provided to ignore the count
value and loop continuously for port testing. Only valid PCI Express control characters/
symbols are allowed for IBIST testing.
Device:
Function: 0
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function: 0
Offset:
Version:
31:24
23:16
15:8
7:0
Bit
Attr
RW
RW
RW
RW
3-2, 0
384h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
7-4
384h
Intel 5000P Chipset
4-5
0
384h
Intel 5000Z Chipset
Default
BCh
B5h
BCh
4Ah
CHARSYM3: Character Symbol [3]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for D10.2.
CHARSYM2: Character Symbol [2]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for K28.5.
CHARSYM1: Character Symbol [1]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for D21.5.
CHARSYM0: Character Symbol [0]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for K28.5.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Register Description