NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 273

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.11.9
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PEX[7:2,0]IBLNS[3:0]: PEX IBIST Lane Status
This register contains the control bits and status information necessary to perate the
Fixed and Open modes of the IBIST logic. The default settings allow the CMM logic to
operate with link width of a PEX port. Only valid PCI Express control characters/
symbols are allowed for IBIST testing.
Device:
Function: 0
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function: 0
Offset:
Version:
6:4
Bit
7
3
2
1
0
RWCST
RWC
Attr
RW
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-7
RO
RO
3-2, 0
393h, 392h, 391h, 390h
393h, 392h, 391h, 390h
Intel 5000P Chipset
RV
4-5
0
393h, 392h, 391h, 390h
Intel 5000Z Chipset
Default
0h
0
0
0
0
1
ERRPTRTYP: Error Symbol Pointer Type
This bit indicates whether or not the errant symbol pointer was a delay symbol
set. If an IBIST engine is implemented with the MISR compare method then this
field is reserved.
0: Errant symbol pointer was a DATA symbol set
1: Errant symbol pointer was a DELAY symbol set
ERRPTR: Error Symbol Pointer
This value indicates which symbol of the 8 possible symbols sent on the lane, as
a set of characters, failed. The value corresponds to position of the set of 8
symbols. If an IBIST engine is implemented with the MISR compare method
then this field is reserved.
IBLOOPSTAT: IBIST Loopback State Status:
This bit is set when the Rx received a TS1 with the loopback bit set. Write a logic
‘1’ to clear.
0: IBIST did not receive a TS1 with loopback bit set.
1: IBIST received a TS1 with loopback bit set.
Reserved.
ERRLNSTAT: Error Lane Status
Error assertion for this lane. Writing a logic ‘1’ will clear this bit. This bit is sticky.
0: No error on this lane
1: Error has occurred on this lane
LNSTREN: Lane Start Enable
When the lane is disabled, no electrical transmissions may occur on the Tx
driver and the receiver’s (Rx) IBIST error reporting is suppressed. This allows
the pattern generator and receiver checking logic to function normally if
required for design simplicity. But it forces a quite Tx lane for adjacent lane
testing.
0: This lane is disabled from IBIST testing, no Tx transmissions and Rx error
reporting is suppressed.
1: Lane enabled. Allows the port start bit to begin IBIST symbol operations on
this lane.
Description
273